Joined: 3 July 2008
Location: FR
Posts: 3

Back to Top

Hello Mark,
Well, in the datasheet section Timing, 't1' corresponds to the minimum clock period witch is 6.9 µs for the Slow Mode. This means that the maximum clock frequency is about 145 KHz. The 6% of errors ,that I had, are with the frequency of 64 KHz (clock frequency), but when I try to increase the frequency I have a lot of errors.

Maybe, like you said, there is a marginal timing in my communication. I didn't find it yet. What I want to do is use the sensor with his maximum capacities. Could you tell me the best frequency of use?

best regards
Dris AGROUR

Joined: 1 February 2006
Location: BE
Posts: 107

Back to Top

Hello

There are actually 2 important items that you need to check, to guarantee robust communications:

- Timings: The max CLK freq is 430 KHz ( high speed mode of 90333) or 145KHz ( low speed mode of 90333). But you should also respect timings t2, t6 and t7

- Application diagram: Check the application diagram, especially the present of the resistors R1,R2 , ... It is important that the signals at chip level are between Vss-Vdd. Especially check at the rising / falling edges of the signals with a scope.

Best regards

Depoorter JC