Joined: 7 July 2008
Location: CH
Posts: 3

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Hello Henry,

The pin MOSI is bi-directional.

A high-level (the recessive level) is set by the external pull-ul resistor (1K).
A low-level (the dominant level) is set either by the Master (ideally through the external MOS transitor) or by the Slave, which is configured in open-drain mode.
This allows bi-directional communication.

You cannot connect directly the FPGA MOSI output directly to the MLX90316, unless the FPGA output is configured (like the MLX90316) in open-drain mode.

For a design more robust to EMC, I advice to implement the application diagram of Fig. 18.

Best regards
Mathieu.