Development & Quality

Internship: Formal verification of digital IPs connected to a SoC communication interface - Paris, France

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Project Description: (3 months)

Formal verification tools give promising methodologies to make electronic designs more reliable. Melexis is looking for an intern to develop a new verification environment leveraging formal methodology to improve the global quality of its digital IPs.

After a familiarization with the Melexis SoC communication interface you will

  • Develop a formal verification environment to assess the correctness of the Melexis digital IPs and to highlight possible design issues.
  • Have to develop a flexible environment, that can be used by other digital designers and for future digital IPs.

Learn/Improve

  • Verilog / System verilog assertion
  • Verification methodology
  • Digital design

Offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our teams.

Inspired Engineering

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