Internship_UVM-MS extension through SystemC-AMS_6 months - Bevaix, Switzerland
Your future internship
As an intern at Melexis, you will work on a
state-of-the-art research to extend UVM with SystemC-AMS libraries with the
objective to drastically improve top level simulation performances.
More specifically, you will:
Explore state-of-the-art proposals, articles, working groups.
Prototype analog/mixed-signals fundamental blocks with SystemC-AMS and create a UVM-MS verification environment to validate the functionality.
Integrate the proposed prototype on a real block of an existing project of a smart sensor device.
- SystemC-AMS modeling guidelines.
- UVM-MS for SystemC-AMS modeled blocks.
- Documentation and presentation.
Good experience in SystemVerilog (UVM).
Experience in SystemC-AMS.
Experience in Cadence MS Suite (not essential but preferred).
Willing to learn.
We offerJoining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our teams. Our Bevaix office is specialized in Hall Sensors and Wireless technology and counts 76 employees.
Facts and Figures
Working Hours per Week
Business Travel Required
Yes, according to position accountabilities
Work Permit Required
Working in Shift Required