Development & Quality

Analog Design Engineer - Nashua (New Hampshire), US





Major Responsibilities

Design and develop the required electronic design and related documentation of the relevant product utilizing our proprietary technology to meet project targets. Take complete ownership of design of assigned blocks from specifications, while ensuring characterization, reliability and testability in the post tape-out (TO) phases. Take ownership of block design and do own layout if layout resources are not available. Complete tasks at the top level of the IC such as IO ring generation etc. Provide guidance to the characterization engineer, test engineer, etc. Take responsibility at the top level of the IC to ensure correct IO, ESD, EMC, and reliability requirements. Design typical analog blocks found in Complementary Metal Oxide Semiconductor (CMOS) mixed-signal ICs. Create transistor level design from specifications and challenge the specifications when needed. Ensure design is insensitive to external factors, such as temperature variation, process variation, background light, etc. Be able to factor in reliability, production test, and Failure Analysis (FA) considerations in own design. Write characterization plans for medium/high complexity chips and use lab equipment to measure and characterize the performance of own block. Be able to analyze simulation results and sift through large amount of IC data, to evaluate performance of blocks or IC.

Job Requirements

Applicant must possess a Master’s degree in Electrical Engineering, Computer Science, Physics or in a related field and 2 years of experience as an Analog Design Engineer in the field of Microelectronics Design, Analysis, and Verification. Additionally, the applicant must have professional experience in the following: 1.) 2 years of experience in designing typical analog blocks found in complementary metal oxide semiconductor (CMOS) mixed-signal ICs (such as op-amps, regulators or LDOs, biasing circuits, ADCs, DACs, switch cap circuits, Phase Lock Loop (PLL) circuits, High speed buffers, etc.); 2.) Experience of 2 complete silicon design cycles including post tape-out (TO) silicon characterization or evaluation phases; 3.) 1 year of experience in configuring the top level of the IC given an IO Library and implementing the IO ring while satisfying ESD Requirements etc.; 4.) 2 years of experience in cadence schematic & layout design tools and familiarity with revision control For IC design; 5.) 1 year of experience in running top level simulations using Analog Mixed-Signal (AMS) mode; 6.) 1 experience of being lead designer for a silicon tape-out (TO); 7.) 1 year of experience in writing characterization plans for medium to high complexity chips; and 8.) 6 months of experience doing layout of own block.


To apply: Send resume via email to Karen Deichmann at

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