Your future job

As an intern at Melexis, you will develop a UVM environment within an existing Simulation Platform.
More specifically, you will:

• Develop/re-use a set of scripts/tools to automatically generate a configurable UVM environment.

• Develop/re-use a set of scripts/tools to integrate SV unit tests within the latter environment.

• Integrate the latter environment within our existing Simulation Platform.

Expected results

• Template for a configurable UVM environment.
• SV Unit test integration.

Requirements

• SystemVerilog, Verilog, UVM; Verilog-AMS is a plus.

• Makefile, Python, Perl, shell scripting.

• Linux and Windows basic knowledge.

• Spoken and written English would be a plus.

We offer

• A challenging job in a dynamic high-tech international environment.

• An enjoyable, team-oriented  and professional  atmosphere in a flat-structured organization.