Development & Quality

Master Thesis_Design and layout of an analog block in SOI CMOS technology - Bevaix, Switzerland

JOB.TITLE

  • OU.DIVISION

  • EMPLOYMENT.TYPE

  • OU.LOCATION




Project Description

As an intern at Melexis, you will work together with the design team to explore a new CMOS technology from XFAB.
You will design an analog block (oscillator, bandgap, low-noise amplifier, voltage regulator…) in order to analyze the performances of this technology for our future magnetic sensor products.

More specifically, you will:

  • Design and simulate an analog block in SOI CMOS technology using Cadence environment.

  • Analyze the performances (noise, PSRR, speed, etc) over temperature and process corners.

  • Make the layout using Cadence Layout XL.

  • Document the block for implementation in a full system.

Expected results

  • Schematics of the designed block

  • Test benches used for verification

  • Layout of the block

  • Design report, analysis of performances versus state-of-the-art blocks

Requirements

  •  Analog design basics
  •  Good English skills
  •  Familiarity with analog CAD environments
  •  Willing to learn
  •  Good communication skills

We offer

  • A challenging Master thesis in a dynamic high-tech international environment

  • The opportunity to take ownership of your professional passion in order to contribute to the success of the company

  • An enjoyable, team-oriented  and professional  atmosphere in a flat-structured organization



Facts and Figures

  • Working Hours per Week

    40

  • Business Travel Required

    According to position accountabilities

  • Work Permit Required

    Yes

  • Working in Shift Required

    No