Development & Quality

Internship - 16 bits Risc-V - 6 months - Paris, France

JOB.TITLE

  • OU.DIVISION

  • EMPLOYMENT.TYPE

  • OU.LOCATION




Project Description

The Risc-V project is intended for 32 and 64 bits CPUs. For very low end products it may be interesting to downgrade it to a 16 bits version. The target of this internship is:
To evaluate the feasibility of a 16 bits version
Highlight the limitations
Estimate the area of such a CPU and compare it to our in-house 16 bits CPUs
Estimate the workload for a modification of the 32 bits C compiler

 

Expected results

  • A Verilog database of the 16 bits Risc-V CPU
  • A test suite in SystemVerilog
  • A report with area, performance and power consumption
  • Few hints on GCC constraints

 

Your profile

  • Master 2

  • Familiar with CPU architectures
  • Basic knowledge of VHDL and/or [System] Verilog

We offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our team. 
Our Paris office is specialized in Digital Design and counts 18 employees.


Facts and Figures

  • Working Hours per Week

    35

  • Business Travel Required

    Yes, according to position accountabilities

  • Work Permit Required

    Yes

  • Working in Shift Required

    No