Development & Quality

Internship - Post Synthesis Helpers - 3 months - Paris, France

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Project Description

Our digital CPU platform makes attentive usage of so-called “helpers” that are SystemVerilog modules aimed at giving valuable human readable information to the verification engineers during the RLT simulations. Unfortunately those helpers are not anymore usable after synthesis. The target of this internship is to work in collaboration with our back-end team and create an automatic port of those helpers into gate level simulations.

 

Expected results

Conversion of exiting helpers into a new form compatible with gate level support
Added support of helpers at gate level
All regression tests passing at RTL and gate level

 

Your profile

  • Master 1

  • Basic knowledge of Verilog and SystemVerilog or at least VHDL

We offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our team. 

Our Paris office is specialized in Digital Design and counts 18 employees.


Facts and Figures

  • Working Hours per Week

    35

  • Business Travel Required

    Yes, according to position accountabilities

  • Work Permit Required

    Yes

  • Working in Shift Required

    No