Internship - Risc-V bus arbiter - 6 to 12 months - Paris, France
The target of this internship is to implement and verify generic bus arbiters and decoder for our next gen. CPU platform (Callisto).
A Verilog design database of the arbiter, a set of SystemVerilog self-testable test cases fully covering the design and a formal proof of the correct behavior of the arbiter.
During this internship you will have the opportunity to gather knowledge on formal proof tools, Python and TCL.
- Master 2
- Basic knowledge of CPU architectures
- Basic knowledge of VHDL and/or [System] Verilog
Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our team.
Our Paris office is specialized in Digital Design and counts 18 employees.
Facts and Figures
Working Hours per Week
Business Travel Required
Yes, according to position accountabilities
Work Permit Required
Working in Shift Required