Internship - Risc-V caches - 6 months - Paris, France
The target of this internship is to evaluate the effect of different cache architectures for "typical Melexis software" on a Risc-V CPU.
During this internship you will have the opportunity to gather knowledge on CPU and cache architecture, use GCC and Cadence tools for linting and simulation.
A comparative list of architectures with their silicon area, maximum operating frequency and software performance improvement.
Basic knowledge of CPU architectures
Basic knowledge of VHDL and/or Verilog
Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our team.
Our Paris office is specialized in Digital Design and counts 18 employees.
Facts and Figures
Working Hours per Week
Business Travel Required
Yes, according to position accountabilities
Work Permit Required
Working in Shift Required