Development & Quality

Internship - Risc-V caches - 6 months - Paris, France

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Project Description

The target of this internship is to evaluate the effect of different cache architectures for "typical Melexis software" on a Risc-V CPU.

During this internship you will have the opportunity to gather knowledge on CPU and cache architecture, use GCC and Cadence tools for linting and simulation.

 

Expected results
A comparative list of architectures with their silicon area, maximum operating frequency and software performance improvement.



Your profile

  • Master 2

  • Basic knowledge of CPU architectures

  • Basic knowledge of VHDL and/or Verilog

We offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our team. 

Our Paris office is specialized in Digital Design and counts 18 employees.


Facts and Figures

  • Working Hours per Week

    35

  • Business Travel Required

    Yes, according to position accountabilities

  • Work Permit Required

    Yes

  • Working in Shift Required

    No