Internship -Self-test program for RISC-V CPUs - 6 months - Paris, France





What we do
Melexis engineers microelectronic solutions. These solutions facilitate the work of our customers. By easy integration. By taking innovation one step further. By providing a competitive advantage. Our technology makes cars and other products smarter, safer and greener. Our sensors capture data from the analog world and comprehend these data digitally. Our drivers make sure customers can bring their products to life. As we always have a plan, we come with the right products at the right moment so our customers stay one step ahead of the competition. That’s what we call inspired engineering.
Who we work for
We mainly focus on semiconductors for the automotive industry. Melexis is energizing the transition to Electrical Vehicles (EVs). We increase the efficiency of Internal Combustion Engine (ICE) cars. Besides the automotive market, we cater to other markets as well.

How we make the difference
Our people are and make the difference. Melexis creates a framework for colleagues to grow, thrive and create impact for themselves, the customer and the company. Because we care, we empower and we excel. We believe in the power of diversity. Spread over 3 continents, 1900 colleagues from 50 nationalities shape the best imaginable future.

Project Description

We are developing circuits that are used in automotive safety critical systems: brakes, steering wheel, cruise control, etc… our circuits must be able to rapidly detect any anomaly in their behavior, flag it to a central ECU and if applicable enter into a safe state. In this context, we want our CPUs to be able to self-test.

There are numerous while challenging ways to realize a CPU self-test. One of them is to create a “small” program taking into account the instruction set architecture and register transfer level description that maximizes the fault coverage with the smallest number of instructions. You will have to analyze each CPU sub-part (ALU, registers…) sensitivity to faults, the impact of malfunctions on the global behavior of the CPU and imagine ways to detect each of them with a self-checking piece of code run by the CPU itself. Compromises between run time, code size and fault coverage will have to be elaborated for the full CPU.

During this internship you will have the opportunity to gather knowledge on CPU architecture, hardware faults, assembler, GCC, Cadence tools for simulation and Synopsys tools for fault injection.


Expected results

  • The target of this internship is to achieve as high as possible fault coverage with the smallest code size for our Risc-V CPU.
  • Optionally also port the methodology to our home made CPUs.

Your profile

  • Master 2
  • Familiar with CPU architectures

We offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our Paris office team which is specialized in Digital Design and counts 20 employees.

Facts and Figures

  • Working Hours per Week


  • Business Travel Required

    Yes, according to position accountabilities

  • Work Permit Required


  • Working in Shift Required